1. Field of the Invention
The present invention relates to a display apparatus and an integrated circuit, and more particularly to a display apparatus including electro-optic elements arranged in a matrix form.
2. Description of the Related Art
In recent years, display apparatuses using electroluminescence elements (hereinafter referred to as EL elements) have been watched as a display apparatus replacing a cathode ray tube (CRT) and a liquid crystal display (LCD). Among them, the application development of an organic EL element, which is a current control type light emitting element, the light emission brightness of which is controlled by a current flowing through the element, has been actively performed. In particular, an organic EL display including its peripheral circuitry uses thin film transistors (TFTs) not only in its display region, but also in the peripheral circuitry.
FIG. 5 illustrates an example of the whole configuration of a conventional display apparatus (organic EL display). In the configuration of FIG. 5, an image display unit (display region) 20 includes a plurality of EL elements 7 and a plurality of pixel circuits 6 for severally driving the EL elements 7. The EL elements 7 and the pixel circuits 6 are arranged in the row direction and column direction of the matrix form in the image display unit 20. Moreover, a data line drive circuit 21 is connected to each column of the image display unit 20 to drive a plurality of data lines 5 for supplying data signals to the pixel circuits 6. Furthermore, a scanning line drive circuit 3 drives a plurality of scanning lines 4 crossing the data lines 5. By the configuration, the display apparatus controls the voltages and currents supplied from the data line drive circuit 21 to the EL elements 7 through the data lines 5 of the respective columns, the time when the voltages and the currents are supplied, and the like, with the signals transmitted from the scanning line drive circuit 3 to the respective pixel circuits 6 through the scanning lines 4 of the respective rows. The brightness of each of the EL elements 7 is adjusted in this manner, and gradation display is performed.
FIG. 4 illustrates the circuit configuration diagram of a pixel of the conventional display apparatus. The circuit configuration shown in FIG. 4 includes one of the pixel circuits 6 using a current setting method, and the circuit operation of the pixel circuit 6 is described by using the current setting method.
The configuration illustrated in FIG. 4 includes the scanning line drive circuit 3, the scanning line 4, driven by the scanning line drive circuit 3, the data line 5, driven by the data line drive circuit 21 (illustrated in FIG. 5), the pixel circuit 6, constituting the image display unit 20, the EL element 7, driven by the pixel circuits 6, a holding capacitor 9 in the pixel circuit 6, a first power supplying line 1 for supplying first electric power (potential) V1 to the image display unit 20, and a second power supplying line 2 for supplying second electric power (potential) V2 to the scanning line drive circuit 3.
Part of the scanning line drive circuit 3 includes a two-stage inverter circuit including p type and n type transistors Tr1 and Tr2, respectively, at the first stage thereof and p type and n type transistors Tr3 and Tr4, respectively, at the second stage thereof, which transistors Tr1 and Tr2, and Tr3 and Tr4 are connected in series with each other at the respective first and second stages between the second power supplying line 2 and the earthing wire GND. Hence, the part of the scanning line drive circuit 3 outputs a signal S2 having the low or high level of the logical levels to the scanning line 4 according to an input signal S1.
The pixel circuit 6 includes a drive transistor (p type TFT) M1, n type transistors (n type TFTs) M2 and M3 as switching elements, the on-off operations of which are controlled by a signal on the scanning line 4, and a p type transistor (p type TFT) M4. The source terminal of the drive transistor M1 is connected to the first power supplying line 1, and the drain terminal thereof is connected to the EL element 7 through the source and drain terminals of the transistor M4. A holding capacitor 9 is connected between the gate terminal of the drive transistor M1 and the first power supplying line 1. The transistor M2 is arranged between the gate terminal of the drive transistor M1 and the drain terminal thereof. The connection point of the drain terminal of the drive transistor M1 and the transistor M4 is connected to the data line 5 through the transistor M3.
When a current signal is set in the pixel circuit 6 in this configuration, a current signal Idata, which is input from the data line 5 into the EL element 7, is transmitted. At this time, a signal S2 on the scanning line 4 is in the high level. Consequently, the transistors M2 and M3 are on, and the transistor M4 is off, so that the drive transistor M1 and the EL element 7 are in non-connected states with each other. Consequently, no currents flow through the EL element 7. Hence, a voltage according to the current driving ability of the drive transistor M1 is generated in the holding capacitor 9 and arranged between the gate terminal of the drive transistor M1 and the first power supplying line 1 by the input current signal Idata.
Next, the signal S2 on the scanning line 4 shifts to a low level, and the transistors M2 and M3 are turned off, and the transistor M4 is turned on. A current according to the voltage held in the holding capacitor 9 is generated by the drive transistor M1, and the current is supplied to the EL element 7. Thereby, the EL element 7 emits light of the brightness according to the supplied current Idata.
The case is examined where the first power supplying line 1 of the pixel circuit 6 and the second power supplying line 2 of the scanning line drive circuit 3 are powered on in that order at the time of power source activation in the display apparatus having the circuit configuration illustrated in FIG. 4. In this case, the potential level of the signal S2 on the scanning line 4 is the low level in the period in which the first power supplying line 1 is powered on and the second power supplying line 2 is not powered on. Consequently, the transistors M2 and M3 are off, and the transistor M4 is on. At this time, if there is an indeterminate potential difference between both ends of the holding capacitor 9, then a current according to the potential difference is generated by the drive transistor M1. Furthermore, since the transistor M4 is on, the drive transistor M1 and the EL element 7 are connected with each other, and the current generated by the drive transistor M1 is supplied to the EL element 7, so that the EL element 7 emits light.
Moreover, the case is examined where the second power supplying line 2 and the first power supplying line 1 are turned off in that order at the time when the power source is turned off. In this case, the potential level of the signal S2 on the scanning line 4 is the low level in the period in which the second power supplying line 2 is powered off and the first power supplying line 1 is not powered off yet, and the transistors M2 and M3 are off and the transistor M4 is on. At this time, since the drive transistor M1 and the EL element 7 are connected to each other, a current according to the potential difference between both ends of the holding capacitor 9 is generated by the drive transistor Ml, and the generated current flows through the EL element 7. As the result, the EL element 7 emits light of the brightness according to the current generated by the drive transistor M1 during the period until the first power supplying line 1 is powered off.
As a unit for preventing the malfunctions at the time of power source activation, Japanese Patent Application Laid-Open No. 2000-105566 describes a display drive integrated circuit equipped with a power source sequence control unit for controlling the order of power source activation. The power source sequence control unit performs the power source sequence control by providing power source connecting switches to power supplying lines.
However, if a switch is provided to a power supplying line capable of making a large current flow, then the power source connecting switch is needed to be enlarged to make the switch itself have a low resistance, and a problem of the enlargement of a circuit area is caused.